Artificial intelligence (AI) and automotive chips are more complex than before. The proportion of edge processing is increasing, and the selection, design, use mode and configuration of storage are becoming more and more difficult.
According to semiconductor Engineering reports that in order to process a large amount of data generated by automotive and AI applications, the chip architecture is becoming more and more complex. In the case of data moving between chips, components and systems and unclear processing priorities, the design team can only strike a balance between merging and sharing storage to reduce costs, or add more different types of storage to improve efficiency and reduce power consumption.
Therefore, there are various methods, including near memory computing, which distributes small storage around the chip or package, and in memory computing, which minimizes data movement. The purpose of these methods is to solve the storage bottleneck and save energy by reducing the load and storage capacity.
Built in SRAM and DRAM storage is still the mainstream of the current market. DRAM has the advantages of high density, simple storage structure, low latency, high efficiency, near infinite access durability and low power consumption. SRAM is very fast, but it is expensive and has limited density. These different requirements will affect the type and quantity of storage and the choice of built-in or external storage.
Power consumption is also the key issue of storage, and different storage types and configurations will also affect the power consumption. For example, moving data on 7-nm process memory requires higher power due to the RC delay of the wire, which may generate heat energy and destroy the integrity of the signal.
Storage is very important to AI, and AI is an important part of all new technologies. But not only the AI chip, but also the AI application inside the chip will affect the use of storage. To achieve ultra high speed and minimum power consumption, the best way is to put all components on the same chip, but sometimes limited by space.
This also explains why AI chips for data centers and training applications are larger than many other types of chips deployed in terminal devices to perform inference applications. Another method is to move part of the storage out of the chip, and design to improve the transmission capacity and shorten the distance from the storage, or limit the data flow of external storage.
The competition of external storage is mainly DRAM-GDDR and HBM. From the engineering and manufacturing point of view, GDDR is similar to other types of DRAM such as DDR and lpddr, which can be put on a standard printed circuit board and use similar processes.
HBM is a relatively new technology, involving stack and silicon interlayer. Each HBM stack has thousands of connections, so it needs high-density interconnection, which far exceeds the processing capacity of PCB. HBM pursues the highest efficiency and best power efficiency, but the cost is higher, which requires more engineering time and technology. GDDR does not have so many interconnections, but it will affect the integrity of the signal.
Farzad zarrifar, director of IP Department of mentor, said that Power, Performance and Area (PPA) are very important, but mainly related to application. Take the portable application as an example, the power is very important, and the power is also divided into dynamic and static parts. If a lot of calculation is needed, the dynamic power is very important; if it is wearable design, the static / leakage power is more important. Electric vehicles care about battery life, so power consumption is also a key factor.
Despite a host of revolutionary technologies and innovative architectures, storage remains at the heart of all design. How to determine the priority, sharing, location and usage of existing storage to obtain the best system performance is a difficult task.
*The content of the article is the author's personal opinion, and does not represent the semiconductor industry's opinion.
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